A predictably low-leakage ASIC design styleJAYAKUMAR, Nikhil; KHATRI, Sunil P.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 3, pp 276-285, issn 1063-8210, 10 p.Article

A METAL and VIA maskset programmable VLSI design methodology using PLAsJAYAKUMAR, Nikhil; KHATRI, Sunil P.IEEE/ACM International Conference on Computer-Aided Design. 2004, isbn 0-7803-8702-3, 2Vol, vol2, 590-594Conference Paper

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm ComputationsPAUL, Suganth; JAYAKUMAR, Nikhil; KHATRI, Sunil P et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 2, pp 269-277, issn 1063-8210, 9 p.Article

Circuit-Level Design Approaches for Radiation-Hard Digital ElectronicsGARG, Rajesh; JAYAKUMAR, Nikhil; KHATRI, Sunil P et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 6, pp 781-792, issn 1063-8210, 12 p.Article

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variationsGULATI, Kanupriya; JAYAKUMAR, Nikhil; KHATRI, Sunil P et al.Integration (Amsterdam). 2008, Vol 41, Num 3, pp 399-412, issn 0167-9260, 14 p.Article